That is not to say that we do not live in interesting times today. With no shortage of high-tech gadgetry in the marketplace, the wave of consumerization in electronics has not only afforded engineers higher visibility and a broader array of end products to work to, but also more demanding time-to-market windows. Being a designer in the 21st century involves far greater complexity than ever before, and our toolbox of tricks includes an ever-increasing range of sophisticated EDA tools and methodologies to accomplish that daunting task. Since 1963, DAC has been the premier showplace for designers to learn about how they can solve the next generation of electronics challenges.

Major DAC themes

This year's DAC boasts a record of 260 exhibitors, along with 160 technical papers, panels, and tutorials. I recently spoke with the 38th DAC General Chair, Jan Rabaey of U.C. Berkeley. DAC has always focused on facilitating interchange among designers, researchers, developers, EDA vendors, and academia, and the DAC Program Committee (led by Professor Rabaey) has placed a spotlight on driving new design tools and methodologies to aid design technology.

This year's DAC is set against a backdrop in which ASIC design capabilities have made the system on a chip (SOC) a reality, albeit both painful and costly. Just as designers are called to "think system" to raise the level of design and verification abstraction, a new wave of physical design tools are changing all the familiar rules -- from logic synthesis to parasitic extraction. Platform-based design is taking root. However, serious issues remain to be overcome in reuse, architecture optimization, interoperability, and verification.

As process technology drills downward towards 100 nanometers and below, optical proximity correction and phase-shift mask techniques have further complicated a device physics and reliability nightmare, where ASIC mask costs are approaching the $1 million mark. To be sure, the cost per function continues to decrease, yet the new ASIC era threatens to become a high-stakes, "rich man's" game. At the same time, these identical process improvements are now enabling FPGA technologies that also support system-on-a-chip design, but without design-specific mask costs. The future is certain to hold new uses for reprogrammability and embedded programmable logic, but what will be realistic? How must EDA tools change to adapt to our evolving needs?

Embedded software is a more traditional view of programmability and is also becoming more tightly coupled into the electronic design process. Engineers are learning that hardware and software skills have more in common than previously thought, yet critical differences between them cannot be overlooked. Digital, analog, RF, and embedded software are merely building blocks for applications, just as an architect must simultaneously understand brick, wood, and stone.

Thus, it is becoming clear that the themes for this year's DAC are centered on system-level and platform-based design, embedded systems, reprogrammable logic and FPGA technology, and advanced circuit techniques -- and the week's program reflects all of this.

For starters, DAC attendees will not want to miss Tuesday's keynote address, "Designing In The New Millennium -- It's Even Harder Than We Thought," featuring Broadcom's co-founder and CTO, Dr. Henry Samueli. Dr. Samueli will share with us an overview of the challenges the design community faces when designing very complex SOCs, specifically addressing how Broadcom is defining their EDA strategy to address these challenges. Broadcom's rapid time-to-market savvy is enabled through the heavy use of design automation tools, coupled with in-house customization and methodology development.

On Thursday, Xilinx president and CEO Willem Roelandts will deliver a keynote entitled "FPGAs Enter The Mainstream." While FPGA technology and design flows have advanced rapidly in recent years, Roelandts will share a preview of even larger technological advancements, such as embedded processors, high-level language support, remote reconfigurable hardware, and fast serial I/Os.

Embedded systems everywhere

Last year, DAC sported an Embedded Systems Day, which this year has been expanded to a full embedded systems design program, reflecting the increased coupling designers face with embedded software and system design issues. This program includes 26 invited presentations, an embedded systems track, and an embedded systems executive panel. Many hardware designers are struggling to adopt platform-based design techniques, in part because of a lack of integration between the software and hardware design flows -- but also because the design community has yet to align on a successful embedded SOC methodology. Reflecting this trend, the Silicon Village from previous DACs has been replaced with an Embedded Showcase, which will feature platforms that incorporate tightly coupled software layers.

All of this should encourage more application engineers to attend DAC, many of whom no longer draw a strong distinction between hardware and software.

The embedded software theme runs throughout this year's show. At the plenary panel entitled, "Embedded System Design: The Real Story," experts from Motorola, Philips, Agere Systems, MontaVista Software, and Magneti Marelli share their user perspective on the increased complexity of embedded systems design, and techniques to cope with such complexity. Attendees will learn how they are applying platform-based design techniques, reconfigurable logic, and reusable software design into an environment with real-time requirements.

Let's get small

If your idea of fun on a Friday night is curling up with a good handbook on device physics, then you won't want to miss the special session looking into the impact of sub wavelength manufacturability on EDA. This panel will explore the changes required for EDA tools to efficiently handle designs employing optical proximity correction and phase shift mask techniques. Or, attend the special session on nanometer futures, which will identify power as the key challenge to all aspects of performance and quality -- in terms of CMOS leakage and scaling limits, not to mention power distribution impact on packaging and integration strategies.

Just when engineers were getting used to dealing with capacitance and resistance as primary constraints on design performance, inductance issues now create brand new signal integrity and delay problems for leading edge designs. The session "Inductance 101 And Beyond" will provide an excellent introduction to the cause and effect of inductance in VLSI circuits, as well as an industry approach to modeling and analyzing the coupling effects of inductance.

Indecisive hardware

Reconfigurable computing has been predicted for years. However, the rapidly rising ASIC mask costs could help accelerate this technology into the mainstream. Tuesday's special session entitled "Reconfiguring The Industry" will feature talks from Chameleon Systems, IMEC, Tensilica, and U.C. Berkeley. The speakers will address how the reconfigurability is dependent upon the application domain, special design techniques, and the concept of reconfiguration at different hierarchical levels. Another session on system-level configurability will focus on bus interfaces and processor design, including hybrid synchronous/asynchronous systems.

As ASIC mask costs continue to rise with each new process generation, there is ever more talk of the FPGA as a replacement technology. The panel session "(When) Will FPGAs Kill ASICs?" delves into this intriguing debate -- a discussion driven by the reality that the newest FPGAs are able to support 1 to 2 million gates, and can now support embedded cores. Listen to experts from LSI Logic, Xilinx, Altera, and others fiercely debate the issues of which technology is destined to win.

SOC/Platform-based design

As platform-based design takes hold across the industry, DAC will highlight successful applications of this methodology. One such special session, entitled "Dissecting An Embedded System: Lessons From Bluetooth," will look at the design process and methodology used by Ericsson for their Bluetooth chip set. Starting from initial specifications through to advanced design verification and test techniques, this case study in the hot wireless-networking arena demonstrates the kind of new methodologies which will be required to push the envelope. Ericsson will also be presenting on challenges for a single-chip implementation of Bluetooth.

One of the biggest challenges for ASIC designers will be explored in the panel session, "Your Core -- My Problem? Integration And Verification of IP." Experts from ARM, Tensilica, Qualis Design, 0-In Design Automation, Tharas Systems, and Co-Design Automation will work towards identifying the best methodologies for successfully integrating reused IP.

And, while we're on the subject of intellectual property -- take note of the paper session describing techniques for IP protection. This will include watermarking, hardware and software metering, and detection.

Many high-end ASIC designers will want to check out the special session on achieving custom IC performance within the realm of the familiar ASIC methodology. Technologists from Lucent, Intel, IBM, and U.C. Berkeley will look at how they stretch the ASIC flow "to the max."

Engineers continue to struggle with how to raise their level of design abstraction. The panel entitled, "If C++ Is The Answer, What Was The Question?" will delve into the value proposition of using C++ for synthesis, validation, test bench generation, and general-purpose modeling. Panelists will address the various C++ offerings and take a critical look at whether these technologies are suitable to satisfy the genuine needs of engineers in this new millennium.

Verification hopes

Run -- don't walk -- to the special session on verification, entitled "Life Beyond Algorithms," where experts from Intel, Motorola, IBM, and Ohio State will share their secrets of verifying cores, system-on-a-chip designs, and even the Pentium IV processor. The speakers will address the nuts and bolts of the techniques used, the resources required to accomplish the job, and the effectiveness of these techniques.

Visualization is an exciting technology for application in VLSI design. A special session on visualization and animation will help engineers understand how to reduce large amounts of data into more meaningful forms, and explain how they catch important sources of errors in clock distribution networks, deep submicron interconnects, and VLSI layouts.

If you're latest design creations are consuming more power than a toaster, perhaps you'll want to visit the power and interconnect analysis session. University researchers are making good progress with energy dissipation, powered network analysis, and optimization.

Analog and mixed-signal

For all of you continuous-time thinkers out there, you'll want to check out the analog design and modeling session. These papers will address data recovery circuits for optical communications systems, behavioral partitioning for synthesis of mixed analog-digital systems, symbolic analysis of large analog circuits, and related exciting topics.

Then, make your way over to the panel session entitled, "When Will The Analog Design Flow Catch Up With Digital Methodology?" Leaders from Cadence, STMicroelectronics, Barcelona Design, Matsushita, Neolinear, and TSMC will uncover the missing key technologies and how these tools must work together in a practical flow.

Best in show

For visitors asking, "What's the best show in town?" the answer is simple: DAC! Just think about it --260 exhibitors, most of whom have waited all year to unleash their latest and greatest product introductions, in hopes that you will grace them with a few minutes of your time. The DAC show floor includes product presentations, rapid-fire demos, and cool giveaways, but also hordes of private demo suites where you can take a deeper look at how these new products can solve your electronic design problems.

Of course, it would be an impossible task to summarize all of the new products being introduced at DAC, however a few vendors have chosen to share some of their new directions. Cadence, for example, is making progress on its ambitious SuperChip roadmap, which was announced back in February. In the verification category, Quickturn will be introducing a flexible emulation platform that mixes custom silicon, simulation, and emulation technologies into a single solution. EDA newcomer Real Intent is introducing features to its Verix verification product, including multi-algorithm formal proof engines for implied and expressed intent, support for VHDL, and a new GUI.

Monterey Design Systems will feature its integration of IC Wizard and Sonar/Dolphin physical design solutions. New EDA start-up Plato Systems is introducing NanoRoute, the industry's first graph-based router. Plato claims that NanoRoute delivers more than 10 times the speed and capacity of the fastest grid-based routers, owing to the new graph technology, as well as algorithms optimized for multiprocessing servers.

Forte Design Systems is featuring a hierarchical verification flow offering new levels of verification flexibility with Quickbench. SynTest Technologies' TurboBIST Logic can check for and automatically repair most BIST violations, allowing at-speed testing of multiple-frequency clock domains and concurrent testing of all clocks in the circuit.

DAC special events

Don't just simply attend DAC -- help set its future direction (in your spare time!) by attending the Accellera annual members meeting and panel discussion. The topic this year is, "Worldwide Users Discuss Design Languages And Methodologies For System Design." Accellera, the unified standards development organization resulting from the merger of VHDL International and Open Verilog International, is looking for a vibrant discussion among real designers.

Finally, DAC is featuring two workshops on Sunday, June 17th. The Interoperability Workshop is a user-driven venue to bring together design system architects from the leading semiconductor, system, and EDA companies hoping to solve critical interoperability problems affecting the business. Organized by Hewlett-Packard, IBM, and Intel, this workshop will feature presentations from LSI Logic, Motorola, STMicroelectronics, SI2, Cadence, Synopsys, Mentor Graphics, Avanti, Magma, and Monterey. The second Sunday workshop focuses on women in electronic design automation, "Smart Risk-Taking -- Innovation." This workshop will share strategies for risk-taking within the boundaries of corporate cultures, and will highlight successes by women in the EDA industry.

Steven E. Schulz is Contributing Editor for ISD Magazine.